The present invention generally relates to the access speed of a semiconductor memory device, typically an SRAM (Static Random Access Memory) device, capable of high-speed reading and, more particularly, to the operational speed of a sense amplifier.
Conventional sense amplifiers use a MOS (Metal Oxide Semiconductor) transistor constitution by taking low power consumption characteristic into consideration. One example of such a constitution was reported by Yoshiyuki Haraguchi, et al. in "1997 Symposium on VLSI Circuits Digest of Technical Papers," p. 80.
However, the semiconductor memory device having a MOS transistor based sense amplifier has a defect of a large (about 20 mV) sense amplifier input offset. In such a constitution, therefore, an operation is kept in a wait state until the signal level on a bit line is raised above that input offset, thereby preventing high-speed reading.
For example, for a sense amplifier having an input offset (20 mV) at which data Q (1 for example) is outputted with ease to output data NQ (0 for example), a read operation must be kept in a wait state until an input signal ND having at least 20 mV appears on the bit line. Therefore, the above-mentioned constitution requires an excess read time as compared with the constitution having an input offset of 0 mV, presenting a problem of being disadvantageous in high-speed reading.